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Three legged NOT gate? What is this symbol?
Different inverter (logic gate) symbolsIGBT Logic SwitchUses for gate expressions, Nor and XorNJM2072D Application Questions for Audio Detection CircuitWhat is the purpose of a buffer gate?How to build AND Gate using transistors?Is it D-Type Flip Flop?What does two input and one output buffer like gate do?XOR gate using simple switchesNot gate that differentiates between 0V and GND
.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty margin-bottom:0;
$begingroup$
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but the third leg is confusing me.
switches logic-gates
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
$endgroup$
add a comment |
$begingroup$
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but the third leg is confusing me.
switches logic-gates
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
$endgroup$
$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
2
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36
add a comment |
$begingroup$
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but the third leg is confusing me.
switches logic-gates
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
$endgroup$
I've come across the above schematic in a datasheet for a 4x2:1 bus switch. What exactly does that triangular symbol on S mean? It looks a lot like a NOT gate, but the third leg is confusing me.
switches logic-gates
switches logic-gates
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
asked Aug 10 at 20:30
Bo ThompsonBo Thompson
1185 bronze badges
1185 bronze badges
$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
2
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36
add a comment |
$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
2
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36
$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
2
2
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36
add a comment |
2 Answers
2
active
oldest
votes
$begingroup$
It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them.
The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that:
You will find these used with differential line drivers.
The following diagram has an issue that the S input bypasses the inverter.
If this logic was used as depicted, the gate connected directly to the S input would switch a fraction faster to the new state then the one which uses the S-NOT from the inverter.
Most manufacturers don't bother with that sort of details. Here is a typical diagram of a 4 output de-mux:
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
$endgroup$
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
add a comment |
$begingroup$
That is a very ambiguous symbol. It probably means that the buffer has both an inverting and non-inverting output. As Tom Carpenter comments it goes to the input of another gate so it must be an output.
There are two common variants of buffers.
A buffer with tri-state output and an enable pin.
A buffer with true and complement outputs. The symbol is usually drawn symmetrically. The virtue of these devices is that there is low timing skew between the two outputs. (I can't find an example at the moment)
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
$endgroup$
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them.
The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that:
You will find these used with differential line drivers.
The following diagram has an issue that the S input bypasses the inverter.
If this logic was used as depicted, the gate connected directly to the S input would switch a fraction faster to the new state then the one which uses the S-NOT from the inverter.
Most manufacturers don't bother with that sort of details. Here is a typical diagram of a 4 output de-mux:
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
$endgroup$
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
add a comment |
$begingroup$
It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them.
The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that:
You will find these used with differential line drivers.
The following diagram has an issue that the S input bypasses the inverter.
If this logic was used as depicted, the gate connected directly to the S input would switch a fraction faster to the new state then the one which uses the S-NOT from the inverter.
Most manufacturers don't bother with that sort of details. Here is a typical diagram of a 4 output de-mux:
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
$endgroup$
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
add a comment |
$begingroup$
It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them.
The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that:
You will find these used with differential line drivers.
The following diagram has an issue that the S input bypasses the inverter.
If this logic was used as depicted, the gate connected directly to the S input would switch a fraction faster to the new state then the one which uses the S-NOT from the inverter.
Most manufacturers don't bother with that sort of details. Here is a typical diagram of a 4 output de-mux:
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
$endgroup$
It is a gate with an inverted and a normal output. The idea is that the two outputs switch exactly at the same time. There is hardly any delay between them.
The symbol as shown in your diagram is rather awkwardly made. More often the following symbol is used for a combined buffer + inverted like that:
You will find these used with differential line drivers.
The following diagram has an issue that the S input bypasses the inverter.
If this logic was used as depicted, the gate connected directly to the S input would switch a fraction faster to the new state then the one which uses the S-NOT from the inverter.
Most manufacturers don't bother with that sort of details. Here is a typical diagram of a 4 output de-mux:
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
answered Aug 11 at 6:24
OldfartOldfart
10.1k2 gold badges9 silver badges30 bronze badges
10.1k2 gold badges9 silver badges30 bronze badges
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
add a comment |
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
$begingroup$
Your answer has inspired me to ask this question.
$endgroup$
– Joel Reyes Noche
Aug 11 at 10:27
add a comment |
$begingroup$
That is a very ambiguous symbol. It probably means that the buffer has both an inverting and non-inverting output. As Tom Carpenter comments it goes to the input of another gate so it must be an output.
There are two common variants of buffers.
A buffer with tri-state output and an enable pin.
A buffer with true and complement outputs. The symbol is usually drawn symmetrically. The virtue of these devices is that there is low timing skew between the two outputs. (I can't find an example at the moment)
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
$endgroup$
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
add a comment |
$begingroup$
That is a very ambiguous symbol. It probably means that the buffer has both an inverting and non-inverting output. As Tom Carpenter comments it goes to the input of another gate so it must be an output.
There are two common variants of buffers.
A buffer with tri-state output and an enable pin.
A buffer with true and complement outputs. The symbol is usually drawn symmetrically. The virtue of these devices is that there is low timing skew between the two outputs. (I can't find an example at the moment)
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
$endgroup$
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
add a comment |
$begingroup$
That is a very ambiguous symbol. It probably means that the buffer has both an inverting and non-inverting output. As Tom Carpenter comments it goes to the input of another gate so it must be an output.
There are two common variants of buffers.
A buffer with tri-state output and an enable pin.
A buffer with true and complement outputs. The symbol is usually drawn symmetrically. The virtue of these devices is that there is low timing skew between the two outputs. (I can't find an example at the moment)
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
$endgroup$
That is a very ambiguous symbol. It probably means that the buffer has both an inverting and non-inverting output. As Tom Carpenter comments it goes to the input of another gate so it must be an output.
There are two common variants of buffers.
A buffer with tri-state output and an enable pin.
A buffer with true and complement outputs. The symbol is usually drawn symmetrically. The virtue of these devices is that there is low timing skew between the two outputs. (I can't find an example at the moment)
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
edited Aug 11 at 15:49
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
answered Aug 10 at 20:41
Kevin WhiteKevin White
14.5k1 gold badge18 silver badges25 bronze badges
14.5k1 gold badge18 silver badges25 bronze badges
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
add a comment |
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
1
1
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
$begingroup$
In this case it is unlikely because the enable signal is an input which is connected in the circuit to another input only.
$endgroup$
– Tom Carpenter
Aug 10 at 22:03
1
1
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
$begingroup$
I agree - that was why I said it is more likely to be a complement output.
$endgroup$
– Kevin White
Aug 10 at 23:53
add a comment |
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$begingroup$
That 3rd (bottom) leg is a copy of the input. Don't know if is buffered or not, though.
$endgroup$
– Dwayne Reid
Aug 10 at 20:35
2
$begingroup$
It is the S input but the symbol is trying to pass on the idea that it has the same delay as the not-output, thus preventing spikes when switching.
$endgroup$
– Oldfart
Aug 10 at 20:36